1. Field of the Invention
The present invention generally relates to a gate structure of a semiconductor device, and a method for forming the same. More particularly, the present invention relates to a method for forming a gate structure of a semiconductor device, which can enhance the refresh property via a process of manufacturing an ultra high integration memory such as 256 megabyte or higher DRAM.
2. Description of the Related Art
Generally, a decrease of the pattern pitch of a transistor for high integration of semiconductors results in a decrease in the threshold voltage of the transistor together with deterioration of a short channel margin. Thus, in order to maintain the threshold voltage Vt for operation of the transistor, ion implantation amount is increased for adjustment of the threshold voltage, thereby increasing the resistance.
In other words, reduction in the size of an identical gate structure for high integration semiconductor devices requires an increase of the ion implantation amount for adjustment of the threshold voltage.
However, the increase of ion implantation amount causes reduction in depth and width of a depletion region at a junction between a source and a drain. A leakage current is increased at the junction, thereby deteriorating the refresh property of the device.
In addition, a planar gate structure with a planar active region has a problem in that the refresh property is further deteriorated upon high integration.